Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs

This book evaluates the influence of process variations and radiation-induced soft errors in FinFET logic cells, considering the 7nm technological node. It adopts a radiation event generator tool and explores four circuit-level techniques to mitigate the effects. It provides a comparison of methods regarding reliability gains and design penalties.

Format: Paperback / softback
Length: 131 pages
Publication date: 11 March 2022
Publisher: Springer Nature Switzerland AG

This comprehensive book delves into the profound impact of process variations and radiation-induced soft errors on a set of logic cells employing FinFET technology, focusing on the 7nm technological node as a case study. To accurately estimate soft errors, the authors employ a radiation event generator tool (MUSCA SEP3), which considers both layout features and electrical properties of devices. Furthermore, they investigate four circuit-level techniques, including transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor, to mitigate the adverse effects on FinFET logic cells. Additionally, the book explores the mitigation tendency when varying process variation, transistor sizing, and radiation particle characteristics are applied in the design. An extensive comparison of all methods addressed in this work is presented, providing insights into the trade-off between reliability gains and design penalties regarding area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section.

This comprehensive book delves into the profound impact of process variations and radiation-induced soft errors on a set of logic cells employing FinFET technology, focusing on the 7nm technological node as a case study. To accurately estimate soft errors, the authors employ a radiation event generator tool (MUSCA SEP3), which considers both layout features and electrical properties of devices. Furthermore, they investigate four circuit-level techniques, including transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor, to mitigate the adverse effects on FinFET logic cells. Additionally, the book explores the mitigation tendency when varying process variation, transistor sizing, and radiation particle characteristics are applied in the design. An extensive comparison of all methods addressed in this work is presented, providing insights into the trade-off between reliability gains and design penalties regarding area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section.

Weight: 238g
Dimension: 235 x 155 (mm)
ISBN-13: 9783030683702
Edition number: 1st ed. 2021