Guide to Computer Processor Architecture: A RISC-V Approach, with High-Level Synthesis

This textbook provides a series of implementations of the RISC-V processor, presented in increasing difficulty, along with corresponding High-Level Synthesis (HLS) codes in C++. It serves as a valuable resource for introducing computer architecture, teaching the RISC-V Instruction Set Architecture, and facilitating FPGA-based development. HLS is emerging as the new standard for IP implementations, and the book is relevant to undergraduates, engineers, and researchers interested in processor implementation and hardware simulators.

Format: Paperback / softback
Length: 439 pages
Publication date: 15 January 2023
Publisher: Springer International Publishing AG

This groundbreaking textbook presents a comprehensive and accessible exploration of the open-source RISC-V processor. It offers a sequential progression of implementations, catering to varying levels of complexity, from non-pipelined to deeply pipelined, multi-threaded, and multicore architectures. Each implementation is presented as High-Level Synthesis (HLS) code in C++, facilitating synthesis and testing on an FPGA-based development board, which can be freely obtained through the Xilinx University Program targeting university professors.

The book serves multiple purposes, making it invaluable for various audiences. Firstly, it offers a novel approach to introducing computer architecture, with the provided codes serving as practical lab exercises for a processor architecture course. Secondly, its content is rooted in the RISC-V Instruction Set Architecture, an open-source machine language that is poised to replace traditional instruction sets such as DLX and MIPS in educational curricula. Thirdly, the designs are implemented using the HLS tool, which enables the translation of C programs into intellectual property (IP). This transition towards HLS is expected to become the new standard for IP implementations, surpassing Verilog/VHDL in popularity.

Furthermore, the textbook/guide caters to engineers and researchers interested in implementing processors on FPGA platforms and in developing RISC-V-based hardware simulators. With the increasing demand for rapid IP development and the emergence of job positions tied to HLS, this resource provides a solid foundation for undergraduates seeking to delve into the world of processor architecture and for professionals seeking to advance their skills in FPGA-based processor implementation and hardware simulation.

Bernard Goossens, a professor in the Faculty of Sciences at the Université de Perpignan, France, is the author of the French-language book from Springer, Architecture et microarchitecture des processeurs, published in 2002. His extensive expertise in the field of computer architecture and his contributions to the textbook make it a valuable resource for students, professionals, and researchers alike.

Weight: 865g
Dimension: 235 x 155 (mm)
ISBN-13: 9783031180224
Edition number: 1st ed. 2023